Joel Rodriguez
135 Alpine |
 Hire USA |
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| Cirrus Logic, Inc.
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 | Design and maintain procedure flow and procedure checklists for tape-out. |
| Execute all R&D tape-out backend verification procedures. |
| Analyze the causes of all backend verification errors to their source and drive corrective actions. |
| Design and maintain design system and cell set regression testing. |
| Design and maintain tape-out design system software and release procedures. |
| Drive quick fix path in software flow for all tape-out critical bugs. |
| Train junior cad engineer. |
| System administration support for tape-out related Sun hardware including the installation and maintenance of Cadence software. |
Accomplishments
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Executed over 400 tape-outs with zero defects. |
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Developed software automating backend verification tasks. |
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Zero defect
award winner (Cell-Set and Mask Technology Team) |
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Designed and implemented a cell status system RDBMS to help evaluate the risks associated with ASIC wafer commitment. |
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Deployed and supported the Magic layout editor for cell set design. |
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Ported various C tools from Sun 3 to Sun 4 platforms. |
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Automated full chip regression testing. |
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Automated cell set regression testing. |
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Developed CMOS
density analysis tool and RDBMS to analyze effects of new technology on
transistor density in ASIC chip design. |
Tool Set
| Magic layout editor, Cadence DFII, Dracula |
| UNIX on Sun. |
| Emacs, Bourne and C Shell Scripts, Makefiles, SCCS, RDBMS |
| C, LISP |
| Proprietary S/LA Design Tools for schematic capture, symbolic layout, net-list generation and physical (CIF) to logical design verification. |
Responsibilities:
| User Support - Answer engineering requests for information about the design system and the S/LA microelement alphabets (CMOS/HMOS) that it supports. Assist engineering in finding effective ways to use the design system. Write meaningful reports on bugs and suggested enhancements. Write special purpose shell scripts, utilities and test programs in C, Unix and/or LISP when required by a particular design project. |
| Quality Assurance - testing, exercising and reviewing the entire design system to verify its proper and robust functioning. |
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Demos - develop a good set of demos of the design system's capabilities, teaching others how to give the demos and on occasional give a demonstration to a customer or interviewee. |
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Product Management - manage the suggested improvements, corrections and additions to the design system including determining user requirements, ascertaining the user's view of their relative priority and defining the optimal functionality of new features and tools. |
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Technology and Error Message Files - Originate, maintain and improve the files that describe Cirrus Logic's S/LA micro alphabet to the design system and manage the details of the user interface. |
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Design Test Circuits - designing and verifying S/LA programs for digital circuits intended as demonstrations of the design system capabilities and as test vehicles of the design system microelement alphabets. |
Accomplishments:
| Defined and executed zero-defect tape-out reviews. |
| Contributed to users at the critical tape-out point by accurately diagnosing design mistakes. |
| Contributed to developers by making specific, straightforward to implement recommendations to improve the software. |
| Contributed to configuration management improving the time required to release new microelements to the design system for tape-out from weeks to 24 hours. |
| Wrote scripts/C code to design test suites for tape-out/cell set QA and verification, covering the range from initial concept to routine use; improving the productivity of both engineering and R&D. |
| Developed system wide disk space usage scripts and databases to support management, moving the disk reorganization project off ground zero. |
| Provided quiet, effective on-call user support reducing the demand for on-call problem support. |
| Improved computing resources for cell set design team by reconfiguring existing Celerity hardware. |
| Cleaned up HP plot-queuing software, making it robust and released to the design system. |
| Pioneered the use of new tools for engineering design teams. |
| Fixed flow control bug (C) in the Apollo port of the symbolic layout editor (GUI). |
| Developed emacs training and trained engineering in the use of emacs. |
Tool Set
| UNIX on Sun & Celerity hardware platforms. Aegis on Apollo platform. |
| Emacs, Bourne and C Shell Scripts, Makefiles, SCCS |
| C, LISP |
| Proprietary S/LA Design Tools for schematic capture, symbolic layout, net-list comparisons and physical to logical design verification (CIF). |
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